1. Field of the Invention
The present invention relates to a method and device for controlling CAS latency, and more particularly to a method and device for precisely controlling a data output timing of the next-generation Double Data Rate (DDR) SDRAM.
2. Description of the Prior Art
As generally known in the art, the higher the operational frequency of a memory device is, the higher the data input/output speeds of the memory device are. However, since a synchronous memory device receives/outputs data in synchronization with a clock signal, the increase of its operational frequency may cause a problem in synchronizing a data input/output timing with a clock signal.
FIG. 1 is a block diagram schematically illustrating the data output control section of a conventional DDR SDRAM.
As shown in FIG. 1, the data output control section includes an internal signal generation unit 110, a CAS latency control unit 120, an output driver 130 and a DLL circuit 140.
The internal signal generation unit 110 receives signals CK,/CS,/RAS,/CAS,/WE etc., applied from an exterior, and generates an internal clock signal clkpd and internal command signals readp and bstendbp which are used in the memory device. Herein, the internal clock signal clkpd is a signal obtained by buffering an external clock signal CK, and ‘clkpd’ is an abbreviation for ‘clock pulse _delayed’. From among the internal command signals, signal ‘readp’ is a signal generated by a read command applied from an exterior and is enabled to a high level when such a read command is applied to the internal signal generation unit 110, and signal ‘bstendbp’ represents the end of read and is generated when a burst ends. For reference, ‘readp’ is an abbreviation for ‘read pulse’, and ‘bstendbp’ is abbreviation for ‘burst end bar pulse’.
The CAS latency control unit 120 generates an output enable control signal suitable to a CAS latency by combining an output signal of the internal signal generation unit 110 and a DLL clock signal dllclkp outputted from the DLL circuit 140. In the following description, an output signal of the DLL circuit 140 is called a DDL clock signal.
The DLL circuit 140 used in a synchronous memory device is a circuit for generating a DLL clock signal dllclkp, and the DLL clock signal dllclkp functions to synchronize a data output timing with an external clock signal CK.
The output driver 130 stores data outputted to an exterior. The output driver 130 outputs stored data to an exterior in synchronization with an DLL clock signal dllclkp while the output enable control signal is enabled to a high level.
For reference, in FIG. 1, ‘tDA’ represents a time period delayed until an output signal of the internal signal generation unit 110 arrives at the CAS latency control unit 120, and ‘tDD’ represents a time period delayed until an output signal of the DLL circuit 140 arrives at the CAS latency control unit 120.
The entire operation of the circuit shown in FIG. 1 is as follows.
When a read command is issued, data read from a memory cell array is stored in the output driver. The data stored in the output driver are outputted to an exterior in synchronization with the clock edge of a DLL clock signal dllclkp while the output enable control signal of the CAS latency control unit is enabled to a high level. The end of a read operation is controlled by a burst end signal.
FIG. 2 is a block diagram illustrating a conventional CAS latency control unit shown in FIG. 1.
The CAS latency control unit shown in FIG. 2 includes a read operation control unit 210 and a data output control signal generation unit 220.
The read operation control unit 210 controls a read operation, and outputs an internal read command signal rd_cmd and a control signal yout. The internal read command signal rd_cmd is a signal for enabling a read operation in the memory device, and the control signal yout is a signal for controlling the operation of the data output control signal generation unit 220.
The data output control signal generation unit 220 receives the control signal yout to generate output enable control signals oe10 to oe50 for adjusting a data output timing. The output enable control signals oe10 to oe50 include information about CAS latency. Therefore, from among the output enable control signals oe10 to oe50, one output enable control signal corresponding to CAS latency is outputted to be applied to the output driver 130 shown in FIG. 1.
For reference, the output signals oe10 to oe50 of the data output control signal generation unit 220 in FIG. 2 correspond to the output enable control signals of the CAS latency control unit 120 in FIG. 1.
FIG. 3 is a waveform view for explaining the operation of the CAS latency control unit shown in FIG. 2.
In FIG. 3, ‘tRD’ represents a delay time from when a read command is applied in synchronization with the rising edge of an external clock signal CK, to when the application of the read command is recognized to generate a signal readp in the memory device. As described with reference to FIG. 1, ‘tDA’ represents a delay time from when an output signal of the internal signal generation unit 110 is outputted to when the output signal of the internal signal generation unit 110 arrives at the CAS latency control unit 120, and ‘tDD’ represents a delay time from when an output signal of the DLL circuit 140 is outputted to when the output signal of the DLL circuit 140 arrives at the CAS latency control unit 120. Also, ‘tCMD’ represents a delay time from when a read command is applied in synchronization with the rising edge of an external clock signal to when an internal read command rd_cmd is generated. In shown in FIG. 3, delay time ‘tCMD’ occurs in synchronization with the rising edge of signal ‘readp’. Finally, ‘tDO’ represents a time difference between the external clock signal CK and the DLL clock signal dllclkp.
In FIG. 3, an output enable control signal OE10 is a signal enabled when the CAS latency is ‘2’, an output enable control signal OE20 is a signal enabled when the CAS latency is ‘3’, an output enable control signal OE30 is a signal enabled when the CAS latency is ‘4’, an output enable control signal OE40 is a signal enabled when the CAS latency is ‘5’, and an output enable control signal OE50 is a signal enabled when the CAS latency is ‘6’.
The data output operation will now be described with reference to FIG. 3.
When a read command is applied from an exterior, an internal read command rd_cmd is enabled after a predetermined period of time elapses.
Next, the CAS latency control unit shown in FIG. 2 generates an output enable signal (e.g., OE10) corresponding to the CAS latency.
Then, while the output enable signal (OE10) is enabled, the output driver (see reference number ‘130’ in FIG. 1) outputs stored data to an exterior in synchronization with the DLL clock signal dllclkp.
Thereafter, when the burst end signal bstendbp is shifted into a low level, the read operation ends.
The above-mentioned data output operation is described for the case in which the CAS latency is ‘2’. When the frequency of the external clock signal CK has a high value, another output enable signal OE30, OE40, etc. to adjust the output timing.
However, as shown in FIG. 3, in order for an DLL clock signal dllclkp generated by the DLL circuit to latch the internal read command rd_cmd, it is necessary to satisfy the following condition:tCMD<tCK−tDO+tDD. 
Herein, ‘tCK’ represents the period of an external clock signal CK.
Since the conventional synchronous memory device which uses an external clock signal having a frequency lower than 500 MHz meets with the above-mentioned condition, a difficulty does not lie in adjusting the data output timing.
However, in the case in which the operational frequency of an external clock signal exceeds 500 MHz, the phase difference between the external clock signal CK and the DLL clock signal dllclkp becomes very small. Furthermore, recent high-speed memory devices have a relation such as ‘tCMD+tDO−tDD>tCK’, which means that it is impossible to properly adjust the data output timing depending on the CAS latency. Accordingly, when the operational frequency of an external clock signal exceeds 500 MHz, the data output operation may malfunction.